#CCOPTS=-fasm -specs bsp_specs -qrtems -O3 -I include -I $(CROSS)/sparc-rtems/include/rtems-ace2 # path to the cross OS installation directoryР”В¬ROSSBIN=/cad/tools/crosscompiler/powerpc-405-linux/bin VPDSYN=$(SCRHOME)/vcdplus-syn-$(notdir $(PWD)) VPDLAY=$(SCRHOME)/vcdplus-lay-$(notdir $(PWD)) VPDRTL=$(SCRHOME)/vcdplus-rtl-$(notdir $(PWD)) # this is the name of synplify target subdirectory # directory containing additional files (IP cores, SW. # directory containing the simulation environment SCRHOME=/scratch/$(USER)/private/tmp/$(TEST_EXAMPLE) # current directory (which is in some cases != $(PWD).) # path to the instantiated verilog blackboxes # path to the instantiated verilog modules # relative to Comrade's 'tests' directory # command to get the directory of the current test example, PRAKTIKUM_BASE=$(COMRADE_ROOT_DIR)/COMRADE/sim_synth/v2pР”В«RAM_VERILOG=$(COMRADE_ROOT_DIR)/COMRADE/sim_synth/platform_independent/bram PRAKTIKUM_BASE=$(COMRADE_ROOT_DIR)/COMRADE/sim_synth/v5 # base directory for MARC, SimEnv, AddOns, etc. PHONY: 'make 'make_target =, timing, rtlsim, rtlsimgui, laysim, ' bits: Generate bitstream (includes ' timing: Generate timing report using timing analyzer (includes ' rtlsim: VCS RTL simulation (text ' rtlsimgui: VCS RTL simulation (interactive gui ' laysim: VCS post-place-and-route simulation (text ' laysimgui: VCS post-place-and-route simulation (interactive gui 'target =, ' ml507: Use Virtex-5 xc5vfx70t-1 as target FPGA (Xilinx ' ml310: Use Virtex-II Pro xc2vp30-6 as target FPGA (Xilinx 'disregard_cache_stalls =, ' 0: for normal ' 1: to disregard cache stalls (results may then be incorrect, but the simulation time without cache stalls is 'physical_synthesis =, ' 0: run Synplify without physical ' 1: run Synplify with physical 'BATCH_GUI =, ' default: run Synplify in batch ' GUI: start Synplify GUI 'toplevel =, datapath, sequencer, hw_kernel, user, plb_marc, ' Sets the toplevel file in the HW design hierarchy relevant for area / timing 'marc =, ' Chooses between usage of MARC1 and MARC2 (use the latter for 256 bit LPU transfers)'Р”Р„REA_TIMING_RESULT_FILE=$(area_timing_result_file)Р”Р„REA_TIMING_RESULT_FILE=area_timing_results.$(target).$(toplevel).txtР”ВISREGARD_CACHE_STALLS=+define+DISREGARD_CACHE_STALLS

Synplify pro power report